root@Ultra96:~/mergejoin# python produce_random_input.py 32
root@Ultra96:~/mergejoin# cat sorted_input.in
1e	1a	
1a	18	
19	16	
14	16	
13	12	
11	11	
f	e	
d	e	
c	e	
b	c	
b	c	
b	c	
5	9	
5	8	
5	3	
3	1	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
0	0	
root@Ultra96:~/mergejoin# echo Bitstream.bin> /sys/class/fpga_manager/fpga0/firmware; dmesg|grep FPGA|tail -1; rm a.out; gcc -O3 -march=native tester.c 2>/dev/null; nice -n -20 taskset 0x4 ./a.out 32
[ 1194.317035] fpga_manager fpga0: writing Bitstream.bin to Xilinx ZynqMP FPGA Manager
M=32
FPGA function...
FPGA time (sec) = 0.00000799000000000000
CPU time  (sec) = 0.00000135000000000000
Speedup = 0.16896120150187735054
	Afrom	Ato	Bfrom	Bto	Key
	===================================
  0|	1	1	0	0	1a	
  1|	5	5	5	5	11	
  2|	8	8	9	b	c	
  3|	f	f	e	e	3	

Validation succeeded!
root@Ultra96:~/mergejoin#