### Welcome to the source code repository for the [paper](https://ieeexplore.ieee.org/document/9695338) "FLiMS: a Fast Lightweight 2-way Merger for Sorting"
The source code is divided into 4 directories. Each directory has its own README.md file for further details.
- ``RTL_generation_and_simulation``
This folder mainly has the python scripts that test and generate Verilog code for FLiMS and the two alternative baselines (WMS and EHMS).
- ``FPGA_implementation_AXI``
This directory includes instructions and AXI-related code to connect the generated Verilog to an AXI interconnect as a peripheral for debugging and evaluating different mergers as an FPGA-based implementation out-of-context.
- ``ARM_Linux_Client_for_Ultra96``
This folder provides an example use case of debugging the mergers generated from ``RTL_generation_and_simulation`` on real hardware. This is to ensure the correct operation as AXI peripherals in real hardware, for trusting the resourse utilisation and performance metrics as reported by Vivado.
- ``SIMD_complete_sorting``
This directory contains the AVX2 implementation of FLiMS (plus bitonic sort) in C/C++ and generator scripts for complete 32-bit sorting in modern processors, to accelerate merge sort.
#### License
[Apache License, Version 2.0](https://opensource.org/licenses/Apache-2.0)
```
Copyright 2021 Philippos Papaphilippou
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
```